1. Field of the Invention
The present invention relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2009-042309, filed Feb. 25, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, demands for high-density semiconductor devices have been increasing with the introduction of IT and the diffusion of mobile devices. Therefore, miniaturization of BGA (Ball Grid Array) semiconductor devices and MCP (Multi Chip Packaging) for packaging multiple stacked semiconductor chips have progressed.
For example, Japanese Patent Laid-Open Publication Nos. 2007-227414 and 2004-111656 disclose BGA semiconductor devices. FIG. 4 illustrates an example of such a BGA semiconductor device.
A BGA semiconductor device 1 shown in FIG. 4 includes: a wiring board 2 having an upper surface 2a with multiple connection pads 3a, 3b, and 3c thereon and a lower surface 2b with multiple lands 4 thereon electrically connected to the respective connection pads 3a, 3b, and 3c; a first semiconductor chip 6 over the surface 2a of the wiring board 2; a spacer 7 stacked over the first semiconductor chip 6; a third semiconductor chip 8 stacked over the spacer 7; a second semiconductor chip 9 stacked over the third semiconductor chip 8; wires 11a, 11b, and 11c; a seal 12 made of an insulating resin covering at least the semiconductor chips 6, 8, and 9, and the wires 11a, 11b, and 11c; and external terminals 5 that are solder balls or the like on the lands 4.
The wiring board 2 is substantially rectangular in plane view (i.e., when viewed in a direction perpendicular to the surfaces 2a and 2b thereof). The wiring board 2 is, for example, a glass epoxy board having a thickness of, for example, 0.25 mm. Wirings (not shown) are provided on both surfaces of the glass epoxy board. The wirings are covered by a solder resist film 14 that is an insulating film having multiple openings (not shown).
The connection pads 3a, 3b, and 3c are provided on the wirings that are on the surface 2a of the wiring board 2 and exposed through the openings of the solder resist film 14. The lands 4 are provided on the wirings that are on the surface 2b of the wiring board 2 and exposed through the openings of the solder resist film 14. The lands 4 are made of, for example, a Cu material, Ni, or Au plating.
The connection pads 3a, 3b, and 3c are electrically connected to the corresponding lands 4 through internal wires 15, penetrating via holes, or the like in the wiring board 2. The lands 4 are arranged in a grid on the surface 2b of the wiring board 2 at a predetermined interval, such as the interval of 0.5 mm.
The first semiconductor chip 6 is disposed over substantially the center of the surface 2a of the wiring board 2 through a fixing member 13, such as an insulating adhesive or a DAF (Die Attached Film). The first semiconductor chip 6 is substantially rectangular in plane view. A predetermined circuit, such as a logic circuit or a memory circuit, is formed on a surface 6a of the first semiconductor chip 6.
Multiple first electrode pads 10a are aligned along sides of the surface 6a of the first semiconductor chip 6. A passivation film (not shown) covers the surface 6a of the first semiconductor chip 6 excluding regions of the first electrode pads 10a to protect the circuit formation surface.
The first electrodes pads 10a on the first semiconductor chip 6 are electrically connected to the corresponding connection pads 3a on the wiring board 2 through the conductive wires 11a made of, for example, Au or Cu. Thus, the first semiconductor chip 6 is electrically connected to the lands 4 through the wires 11a, the connection pads 3a, and the internal wires 15.
The spacer 7 is stacked over the first semiconductor chip 6 through the insulating fixing member 13. The third semiconductor chip 8 is stacked over the spacer 7 through the insulating fixing member 13.
Multiple third electrode pads 10c are aligned along sides of an upper surface 8a of the third semiconductor chip 8. A passivation film (not shown) covers the surface 8a of the third semiconductor chip 8 excluding regions of the third electrode pads 10c to protect the circuit formation surface.
The third electrode pads 10c on the third semiconductor chip 8 are electrically connected to the corresponding connection pads 3c on the wiring board 2 through the conductive wires 11c. 
The second semiconductor chip 9 is stacked over the third semiconductor chip 8 through the insulating fixing member 13. Multiple second electrode pads 10b are aligned along sides of an upper surface 9a of the second semiconductor chip 9. A passivation film (not shown) covers the surface 9a of the second semiconductor chip 9 excluding regions of the second electrode pads 10b to protect the circuit formation surface.
The second electrodes pads 10b on the second semiconductor chip 9 are electrically connected to the corresponding connection pads 3b on the wiring board 2 through the conductive wires 11b. 
The seal 12 covers substantially the entire surface 2a of the wiring board 2 so as to cover the semiconductor chips 6, 8, and 9, and the wires 11a, 11b, and 11c. The seal 12 is made of a thermosetting resin, such as an epoxy resin. The seal 12 has a thickness of approximately 400 μm.
As the external terminals 5, solder balls that are bumps are mounted in a grid on the corresponding lands 4 on the surface 2b of the wiring board 2.
Recently, demands for packaging a radio frequency (RF) chip together with a memory chip and a logic chip have been increasing with the progress of BGA semiconductor devices having a multi-chip packaging structure.
The radio frequency chip is likely to generate high frequency noises outside the chip compared to other semiconductor chips. Additionally, the radio frequency chip is likely to malfunction if subjected to radio frequency noises or noises caused by a power source variation. The memory chip consumes much current in a wiring operation, and therefore noises caused by a power source variation are likely to be generated.
FIG. 3 illustrates variations in voltages of a power source and the ground of the memory chip. As understood from FIG. 3, the power source in the memory chip and the potential of the ground are not stable in an actual operation, thereby causing a variation in voltage if a large amount of current flows in a memory writing process or in an output switching process.
To reduce the variation in voltage and to prevent malfunction of the chip, it is effective to reduce impedance of the power source or the ground. As general countermeasures, the widths of wirings of the power source and the ground are increased to increase capacity. Additionally, multiple wiring paths are provided to reduce the resistance. Alternatively, a decoupling capacitor for preventing power noises is inserted.
However, these countermeasures cannot be taken for high-density semiconductor devices. To package the radio frequency chip together with the memory chip and the like, the effects of radio frequency noises have to be prevented. For this reason, various countermeasures, such as an increase in distance among chips, and design and preproduction of shields and substrate wirings, are required so as not to cause characteristic defects.
Further, various countermeasures for reducing impedance are required so as to prevent noises caused by a power source variation. However, no effective countermeasure has been proposed.